I'm a PhD-student in Security on Hardware Architecture for Embedded Systems. My PhD thesis is part of the SCRATCHS project. The aim of the SCRATCHS project is to co-design a RISC-V processor and a compiler toolchain to ensure by construction that a security sensitive code is immune to timing side-channel attacks while running at maximal speed.

In this project, I am in charge of the hardware side, where we are mitigating the timing side channels that are contained in the micro-architectural features of the RISC-V core and those that are induced by the cache. See Publications section for more details.