I'm a IC degital designer with a focus on RISC-V Architecture, Cryptography and Performance-ended IPs. IPs are embed in a low area context with the threat of Side Channel Attacks and Fault Injection Attacks.

Graduated with a PhD in the field of Security on Hardware Architecture for Embedded Systems. My PhD thesis is part of the SCRATCHS project. The aim of the SCRATCHS project is to co-design a RISC-V processor and a compiler toolchain to ensure by construction that a security sensitive code is immune to timing side-channel attacks while running at maximal speed.

In this project, I was in charge of the hardware side, where we were mitigating the timing side channels contained in the micro-architectural features of the RISC-V core and those that are induced by the cache. See Publications section for more details.